Probing the Design - 2021.2 English

Probing the Design - 2021.2 English - UG949

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID

UG949

Release Date

2021-11-19

Version

2021.2 English

The Vivado tools provide several methods to add debug probes in your design. The table below explains the various methods, including the pros and cons of each method.

Table 1. Debugging Flows
Debugging Flow Name	Flow Steps	Pros/Cons
HDL instantiation probing flow	Explicitly attach signals in the HDL source or IP-Integrator canvas to an ILA debug core instance.	You have to add/remove debug nets and IP from your design manually, which means that you will have to modify your HDL source. This method provides the option to probe at the HDL design level. Allows for probing certain protocols such as AXI or AXI4-Stream at the interface level It is easy to make mistakes when generating, instantiating, and connecting debug cores.
Netlist insertion probing flow	Use one of the following two methods to identify the signal for debug: Use the MARK_DEBUG attribute to mark signals for debug in the source RTL code. Use the MARK_DEBUG right-click menu option to select nets for debugging in the synthesized design netlist. Once the signal is marked for debug, use the Set up Debug wizard to guide you through the Netlist Insertion probing flow.	This method is the most flexible with good predictability. This method allows probing at different design levels (HDL, synthesized design, system design). This method does not require HDL source modification.
Tcl-based netlist insertion probing flow	Use the `set_property` Tcl command to set the MARK_DEBUG property on debug nets then use netlist insertion probing Tcl commands to create debug cores and connect them to debug nets.	This method provides fully automatic netlist insertion. You can turn debugging on or off by modifying the Tcl commands. This method does not require HDL source modification.