Creating Pblocks for Versal Devices - 2021.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2021.2 English
As part of improvements to the Versal architecture, the smallest unit that can be reconfigured is much smaller than in previous architectures. The minimum required resources for reconfiguration varies based on the resource type, and are referred to as a Programmable Unit (PU). Many site types have improved PU requirement making granularity of reconfigurable Pblocks significantly improved compared to previous architecture.
Tip: While the fundamental building blocks are shown in the following images, in real design scenarios they will be part of a larger collection of resources, creating a comprehensive floorplan for each dynamic region.
The following are the details provided for each site type:
Programmable Logic (PL) NoC NMU and NSU: PU is the corresponding NOC_NMU or NOC_NSU tile.
Figure 1. PL NoC NMU and NSU
CLE: Two adjacent CLE tiles share a routing resource (interconnect tile). PU is 2 CLE tiles (4 SLICE sites) with shared interconnect.
Figure 2. CLE PU
BRAM: PU is the corresponding BRAM tile. One BRAM tile includes two RAMB18s and one RAMB36. Adjacent INTF and INT tiles are automatically pulled into the routing footprint if it is not covered by the Pblock. Unlike previous architecture, adjacent CLE sites are not part of BRAM PU.
Figure 3. BRAM PU: RAMB18s and RAMB36 of 1 BRAM Tile
URAM: PU is the corresponding URAM tile. One URAM tile includes only 1 URAM site. Adjacent INTF and INT tiles are automatically pulled into the routing footprint if it is not covered by the Pblock.
Figure 4. URAM PU: URAM Tile
DSP: PU is the corresponding DSP tile. One DSP tile includes 2 DSP sites.
Figure 5. DSP PU: DSP Tile
IRI_QUAD (ODD/EVEN): PU is the corresponding INTF_ROCF_TL_TILE. One tile includes 4 IRI Quads. INTF at the center of IRI quads is automatically pulled into routing footprint. Though IRI_QUADs are user range-able, adjacent IRI_QUADs of RP Pblock are automatically pulled in to the routing footprint since expanded routing footprint is always 2 INT tile expansion.
Figure 6. Imux Register Interface Quad: PU is INT_ROCF_TL Tile
PCIe 40: PU is the corresponding PCIEB_BOT_TILE. Adjacent INTF tiles are automatically included in the routing footprint of reconfigurable Pblock.
Figure 7. PCIe 40 PU is PCIe Tile