The Versal PCI Express® Integrated Block in Vivado supports link debug. If enabled, the core will store the Link Training and Status State Machine (LTSSM) state transitions which is accessible in the Vivado Hardware Manager.
The Versal PCI Express® Integrated Block in Vivado supports link debug. If enabled, the core will store the Link Training and Status State Machine (LTSSM) state transitions which is accessible in the Vivado Hardware Manager.