Information Reuse - 2021.2 English

Reuse information from a design that met timing. Use this flow if the design does not consistently meet timing. To reuse information:

1. Open two implementation runs:
   1. One for a run that is meeting timing.
   2. One for a run that is not meeting timing.
      Tip: On a computer with multiple monitors, select Open Implementation in New Window to open a design in a new window.
2. Look for the differences between the two designs.
   1. Identify some failing timing paths from report_timing_summary.
   2. On the design that is meeting timing, run report_timing in min_max mode to time those same paths on the design that meets timing.
3. Compare the timing results:
   1. Clock skew
   2. Datapath delay
   3. Placement
   4. Route delays
4. If there are differences in the amount of logic delay between path end points, revisit the synthesis runs.