The Global Clock Source Details table shows the global clock connectivity and timing clock information for each clock generator output. The following figure shows the connectivity of each output of an MMCM (src0/src1) to clock buffers. The output CLKOUT0 of src1 drives two global clocks g7 and g8.
Figure 1. Report Clock Utilization – Global Clock Source Details Table
The columns in the Global Clock Source Details table are listed in the following table.
| Column | Description |
|---|---|
| Source Id | ID of the clock generating primitive. |
| Global Id | Global clock ID(s) driven by the Global Clock source pin. |
| Driver Type/Pin | Output primitive pin which generates the clock. |
| Constraint |
User physical constraint with highest precedence applied to the clock buffer. Priority rule is as follows:
|
| Site | Global clock source location set by the user or by the Vivado implementation tools. |
| Clock Region | Device clock region where the clock source is located. |
| Clock Loads | Number of clock pin loads connected to Global Clock source pin. |
| Non-Clock Loads | Number of non-clock pin loads, such as FDCE/CE pins for example. |
| Source Clock Period | Period in ns of the timing clock generated by the Global Clock Source pin. If several clocks propagate on the same clock net, the smallest clock period is reported. |
| Clock | Name of the timing clock generated by the Global Clock Source pin. If several clocks propagate on the same clock net, "Multiple" is reported. |
| Driver Pin | Logical name of the Global Clock Source pin. |
| Net | Logical name of the clock net segment connected to the Global Clock Source pin. |