Vitis Model Composer Tutorial (UG1498) - 2021.2 English

Document ID: UG1498
Release Date: 2021-11-29
Version: 2021.2 English

Revision History
Locating the Tutorial Design Files
HDL Library
Lab 1: Introduction to Vitis Model Composer HDL Library
Step 1: Creating a Design in an FPGA
Configure the HDL Blocks
Review the Results
Step 2: Creating an Optimized Design in an FPGA
Step 3: Creating a Design using Discrete Components
Step 4: Working with Data Types
Part 1: Designing with Floating-Point Data Types
Part 2: Designing with Fixed-Point Data Types
Summary
Lab 2: Importing Code into a Vitis Model Composer HDL Design
Step 1: Modeling Control with M-Code
Step 2: Modeling Blocks with HDL
Step 3: Modeling Blocks with C/C++ Code
Part 1: Creating a Vitis HLS Package
Part 2: Including a Vitis HLS Package in a Vitis Model Composer Design
Summary
Lab 3: Timing and Resource Analysis
Step 1: Timing Analysis in Vitis Model Composer
Troubleshooting Timing Violations
Step 2: Resource Analysis in Vitis Model Composer
Summary
Lab 4: Working with Multi-Rate Systems
Step 1: Creating Clock Domain Hierarchies
Step 2: Creating Asynchronous Channels
Step 3: Specifying Clock Domains
Summary
Lab 5: Using AXI Interfaces and IP Integrator
Step 1: Review the AXI Interfaces
Step 2: Create a Vivado Project using Vitis Model Composer HDL IP
Step 3: Create a Design in IP Integrator
Step 4: Implement the Design
Summary
Lab 6: Using a Vitis Model Composer HDL Design with a Zynq-7000 SoC
Step 1: Review the AXI4-Lite Interface Drivers
Step 2: Developing Software and Running it on the Zynq-7000 System
Summary
HLS Library
Lab 1: Introduction to Model Composer HLS Library
Procedure
Step 1: Review the HLS Library
Access the HLS Library
Step 2: Build Designs with HLS Blocks
Sobel Edge Detection: Algorithm Overview
Implementing Algorithms in Vitis Model Composer
Step 3: Work with Data Types
Work with Native Simulink Data Types
Convert Data Types
Convert Data Types (Alternative)
Additional Details
Conclusion
Lab 2: Importing Code into Vitis Model Composer
Step 1: Set up the Import Function Example
Step 2: Custom Blocks with Function Templates
Conclusion
Lab 3: Debugging Imported C/C++-Code Using GDB Debugger
Step 1: Set Up the Example to Debug the Import Function
Step 2: Debugging C/C++ Code Using GDB Debugger
Conclusion
Lab 4: Automatic Code Generation
Procedure
Step 1: Review Requirements for Generating Code
Step 2: Mapping Interfaces
Step 3: Generate IP from the Vitis Model Composer Design
Step 4: Generate HLS Synthesizable Code
Step 5: Port a Vitis Model Composer HLS Design to HDL Design
Conclusion
AI Engine Library
Vitis Model Composer for AI Engine Lab Overview
Lab 1: Importing AI Engine Kernels
Procedure
Step 1: Build the AI Engine Design in Vitis Model Composer
Step 2: Simulate the Design
Step 3: Code Generation and Running AI Engine SystemC Simulation
Conclusion
Lab 2: Importing AI Engine Graphs
Procedure
Step 1: Build an AI Engine Design using Graph Code
Step 2: Simulate the Design
Step 3: Code Generation and AI Engine SystemC Simulation
Conclusion
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Please Read: Important Legal Notices

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