Free Running Pipeline - 2021.2 English

Vitis HLS Messaging (UG1448)

Document ID
UG1448
Release Date
2021-10-27
Version
2021.2 English

Description

Warning: [HLS 200-1970] Disabling free running pipeline (frp) architecture on pipeline 'VITIS_LOOP_26_1' in module 'top', because it has a registered FIFO input port:A

Explanation

Registered FIFO ports are not supported inside an FRP pipeline.

void buff2stream(unsigned int nblocks, hls::stream_of_blocks<block8x8> &i_buff, hls::stream<float> &stream)
{
    hls::read_buf<block8x8> buff(i_buff);

    buff2stream_l_flat: stream2buff_l_flat: for(int k=0; k<nblocks*64; k++) {
#pragma HLS loop_tripcount min=512*64 max=32400*64
#pragma HLS PIPELINE II=4 rewind
#pragma HLS unroll factor=4
    int n=k/64;
    int i=k%64;
    if (i == 0) {
      buff.acquire();
}
  stream.write(buff[i]);
      if (i == 64-1) {
      buff.release();
    }
  }
}