Manually Copying Generated Mirror Module into the User Project Directory - 2021.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)
Document ID
UG1393
Release Date
2022-03-29
Version
2021.2 English
  1. The sources for the mirror module are generated along with the IP sources while generating XCLBIN. If you do not wish to manually write the code for the modules, use and copy these source files.
  2. Locate the <vivado_project_dir>/<project_name>/<project_name>.gen directory.
  3. Run the following find command to return a list of generated files for the sim_ipc mirror modules:
    find . -regextype grep -regex ".*\/export\/.*\.\(h\|cpp\|sv\).user"

    This returns a list of file in the following format:

    ./sources_1/bd/<design_name>/ip/<module_name>/export/<module_name>_mirror.cpp.user, 
    ./sources_1/bd/<design_name>/ip/<module_name>/export/<module_name>_mirror.h.user, 
    ./sources_1/bd/<design_name>/ip/<module_name>/export/<module_name>_mirror.sv.user
  4. Copy these files to the user project area while renaming the files with .user suffix removed. Note that three files are generated for each module. The SystemC implementation in .h, .cpp, and a .sv file containing the system Verilog stub module definition.
  5. Copy the four utility source files from https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/emulation/external_traffic_generator/example/utils into the user project directory.
  6. Write a compilation, elaboration, and simulation script using the following as a guide: https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/emulation/external_traffic_generator/example/utils/run.sh.