Streams of 4K UHD at 60 Hz consume significant amounts of the bandwidth of the external memory interfaces and significant amounts of the Arm® AMBA® AXI4 bus bandwidth between the Processing System and the Programmable Logic.
For simultaneous encoder and decoder operation (including transcode use cases), consider using both a Xilinx PS Memory Controller and dedicated a Xilinx VCU Memory Controller.
| Number of stream | Single stream | Two stream | Four stream |
|---|---|---|---|
| CLB LUT (230400) | 16224 | 18302 | 21178 |
| CLB Registers (460800) | 21098 | 24175 | 30339 |
| Carry8 (28800) | 1316 | 1417 | 1620 |
| F7 Muxes (11520) | 105 | 105 | 119 |
| F8 Muxes (57600) | 0 | 0 | 12 |
| BLOCK RAM TILE (312) | 8 | 8 | 8 |
| DSP's (1728) | 0 | 0 | 0 |
| HPIOBDIFFINBUF (192) | 0 | 0 | 0 |
| BITSLICE_RX_TX (416) | 0 | 0 | 0 |
| GLOBAL CLOCK BUFFERS (544) | 0 | 0 | 0 |
| PLL (16) | 0 | 0 | 0 |
| MMCM (8) | 0 | 0 | 0 |