The following figure shows the block diagram of VCU DDR4 Controller which has five AXI ports, s_axi_clk, s_axi_rst, c0_sys_clk, and sys_rst.
Figure 1. AXI Clock Port / Reset Port Connection
S_AXI_CLK / S_AXI_RST: The AXI ports work with respect to this clock and reset. Active-Low reset is used.
C0_SYS_CLK / SYS_RST: This is the actual clock used for VCU DDR4 controller, which is of frequency 125 MHz for x16 configuration and 300 MHz for x8 configuration. Active-Low reset is used.