The Xilinx® Zynq® UltraScale+™ MPSoC architecture-based FPGAs VCU DDR4 IP v1.1 core is a combined pre-engineered controller and physical layer (PHY) for interfacing Zynq UltraScale+ MPSoC programmable logic (PL) user designs to DDR4 SDRAM. This DDR4 Controller is only for use with the Zynq UltraScale+ MPSoC EV products and not for us with any other Xilinx devices.
This chapter provides information about using, customizing, and simulating a LogiCORE™ IP DDR4 SDRAM for Zynq UltraScale+ MPSoCs. It also describes the core architecture and provides details on customizing and interfacing to the core.