The Decoder (VDEC) and Encoder (VENC) blocks work independently as separate units without any dependency on each other. The following table describes the clock domains in VCU core.
| Domain | Max Freq (MHz) | Description |
|---|---|---|
| Core clock | 712 | Processing core, most of the logic and memories |
| MCU clock | 444 | Internal micro controllers |
| AXI Master Port clock | 333 |
AXI master port for memory access, 128-bit, typically connected to PS AFI-FM (HP) port or to a soft memory controller in the PL. |
| AXI4-Lite slave port clock | 167 |
s_axi_lite_aclk,
AXI4-Lite slave port (32-bit)
for register programming |
m_axi_mcu_aclk is
asynchronous to all clocks used in VCU.The following figure shows the clock generation options inside VCU block. Note that the following blocks work on a single clock domain:
-
pll_ref_clkis sourced externally to the device, typically by a programmable clock integrated circuit. - Video encoder and decoder blocks work under the
VENC_core_clkdomain generated by the VCU PLL. - MCU for encoder and decoder work under the
VENC_MCU_clkdomain generated by the VCU PLL. -
m_axi_enc_aclkis the AXI clock input from the PL for the 128-bit AXI master interfaces for the encoder. -
m_axi_dec_aclkis the AXI clock input from the PL for the 128-bit AXI master interfaces for the decoder. -
s_axi_lite_aclkis the AXI4-Lite clock from the PL. -
m_axi_mcu_aclkis the MCU AXI master clock from the PL.Figure 1. Clock Generation Options
The following clock frequency requirements must be met while providing clocks from PL:
- The AXI clock for encoder and decoder interface is limited to 333 MHz.
- The following ratio requirements need to be met:
-
s_axi_lite_aclk≤ 2 ×m_axi_enc_aclk -
s_axi_lite_aclk≤ 2 ×m_axi_dec_aclk
Refer to Microcontroller Unit Overview for more information on the MCU.
-
The VENC_core_clk is generated based
on the VCU PLL.
The VENC_MCU_clk is generated based
on the VCU PLL.
The VDEC_core_clk is generated based
on the VCU PLL.