RAM32X1S - 2021.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
Release Date
2021.1 English

Primitive: 32-Deep by 1-Wide Static Synchronous RAM

  • Families: UltraScale, UltraScale+


This design element is a 32-bit deep by 1-bit wide static random access memory with synchronous write capability. When the write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When (WE) is High, any positive transition on (WCLK) loads the data on the data input (D) into the memory cell selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs must be stable before a Low-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). However, (WCLK) can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by the values on the address pins.

You can use the INIT attribute to specify the initial contents of the RAM. If left unspecified, the initial contents default to all zeros.

Logic Table

Inputs Outputs
WE (Mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) D D
1 (read) X Data

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT HEX Any 32-bit value All zeros Specifies the initial contents of the RAM.
IS_WCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the WCLK pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
--           UltraScale
-- Xilinx HDL Language Template, version 2021.1

RAM32X1S_inst : RAM32X1S
generic map (
   INIT => X"00000000", -- Initial contents of RAM
   IS_WCLK_INVERTED => '0') -- Specifies active high/low WCLK
port map (
   O => O,       -- RAM output
   A0 => A0,     -- RAM address[0] input
   A1 => A1,     -- RAM address[1] input
   A2 => A2,     -- RAM address[2] input
   A3 => A3,     -- RAM address[3] input
   A4 => A4,     -- RAM address[4] input
   D => D,       -- RAM data input
   WCLK => WCLK, -- Write clock input
   WE => WE      -- Write enable input

-- End of RAM32X1S_inst instantiation

Verilog Instantiation Template

// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM (Mapped to a LUT6)
//           UltraScale
// Xilinx HDL Language Template, version 2021.1

RAM32X1S #(
   .INIT(32'h00000000),    // Initial contents of RAM
   .IS_WCLK_INVERTED(1'b0) // Specifies active high/low WCLK
) RAM32X1S_inst (
   .O(O),       // RAM output
   .A0(A0),     // RAM address[0] input
   .A1(A1),     // RAM address[1] input
   .A2(A2),     // RAM address[2] input
   .A3(A3),     // RAM address[3] input
   .A4(A4),     // RAM address[4] input
   .D(D),       // RAM data input
   .WCLK(WCLK), // Write clock input
   .WE(WE)      // Write enable input

// End of RAM32X1S_inst instantiation

Related Information

  • See the UltraScale Architecture Configurable Logic Block User Guide (UG574).