Vivado Design Suite Tutorial: Logic Simulation (UG937) - 2021.1 English - Introduces the Vivado® simulator to interactively simulate and debug Xilinx® FPGA designs in the Vivado Integrated Design Environment (IDE). The Vivado simulator is an HDL simulator that lets you perform behavioral, functional, and timing simulations for VHDL, Verilog, and mixed-language designs. - UG937

Document ID

UG937

Release Date

2021-07-14

Version

2021.1 English