Hold/Removal (Min Delay Analysis) - 2021.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
Release Date
2021.1 English
  • source clock (Slow_min), datapath (Slow_min), destination clock (Slow_max)
  • source clock (Fast_min), datapath (Fast_min), destination clock (Fast_max)

Delays from different corners are never mixed on a same path for slack computation.

Most often, setup or recovery violations occur with Slow corner delays, and hold or removal violations occur with Fast corner delays. However, since this is not always true (especially for I/O timing) Xilinx recommends that you perform both analyses on both corners.