Supported Features - 2021.1 English - UG900

Limited by other language features such as generic package which XSIM does not yet support. Not all newly added std functions are supported.

Notably, stop and finish are supported.

?=, ?/=, ?>, ?>=, ?<, ?<=

x ?= y

signal x: std_logic_vector(0 to 31);
signal x_and : std:logic;
...
x_and <= and x;

case x and y is
    when '1' => report "1";
    when '0' => report "0";
end case;

Instead of an intermediate variable or signal, we can use an expression directly in the case statement.

signal s : std_logic;
signal v, r : std_logic_vector(0 to 7);
...
r <= s and v;

16SX"FF” = "1111_1111_1111_1111”

16UX”FF” = “0000_0000_1111_1111”

process(clk)
...
    with x select
        y := "111" when "110",
            "000" when others;
    a := '1' when b = '1' else
        '0' when b = '0';
...

type areaOfSquare is protected
    procedure setx(newx : real);
    impure function area return real;
end protected;

type areaOfSquare is protected body
variable x : real = 0.0;
...

Protected type shared variable is supported in HDL simulation, but Tcl and GUI does not allow examining value of protected type shared variables yet.

type bit_word is array (natural range <>) of bit;
function resolve_array (s : bit_word) return bit;
subtype resolved_array is (resolve_array) bit_word;

/*
X <= 1;
process(all)
...
*/

Sentity test is
    generic (type data_type);
    port (
        x : in data_type;
        s : out data_type);
end entity test;