Enabling or Disabling Interactive DRCs - 2021.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
Release Date
2021.1 English

During I/O planning, the Vivado IDE runs basic checks to ensure a legal pinout. However, complete sign-off DRCs are only run during Vivado implementation. Therefore, you need to run your design through Vivado implementation to ensure final legal pinouts.

The interactive I/O placement routines check common error cases during pin placement. You can toggle this capability on and off with the Autocheck I/O Placement checkbox in the General tab of the Package window settings.

When you enable automatic checking, the tool does not allow placement of I/O ports on pins that cause a design issue. In Place I/O Ports Sequentially mode, if you attempt to place an I/O Port on a problematic pin, a tooltip appears that describes why the I/O port cannot be placed. The interactive DRCs are enabled by default.

Important: Many of these DRCs are only run on a synthesized or implemented design.

The interactive I/O placement rules include:

  • Placement on noise-sensitive pins associated with GTs or on I/O package pins that are potentially noise-sensitive
  • I/O standard violations
  • I/O standards are not used in banks that do not support them
  • Banks do not have incompatible VCC ports assigned
  • Banks that need VREF ports have free VREF pins
  • Proper assignment of global clocks and regional clocks (only with an imported netlist and XDC file)
  • Differential I/O ports are set to the proper sense pin
  • No output pins are placed on input-only pins
Recommended: Xilinx recommends that you begin your I/O port placement with DRCs enabled. See the device documentation for more information on I/O ports and clock region specifications.