Synthesize the Design and Insert the ILA Core - 2020.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

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2020.2 English

The next step is to synthesize the top-level design. To do this:

  1. Select Flow Navigator > Synthesis, and click Run Synthesis.

    After synthesis finishes, the Synthesis Completed dialog box opens.

  2. Select Open Synthesized Design to open the netlist design, and click OK.

    The Schematic and the Debug window opens. If the Debug window at the bottom of the GUI is not open, you can always open that window by choosing Windows > Debug from the menu. The following figure shows the Debug window.

    You can see all the nets that were marked for debug in the Debug window under the folder Unassigned Debug Nets. These nets need to be connected to the probes of an Integrated Logic Analyzer (ILA). This is the step where you insert an ILA core and connect these unassigned nets to the probes of the ILA.

  3. Click the Set up Debug button in the Debug window toolbar.

    Alternatively, you can also select Tools > Set Up Debug, shown in the following figure.

    The Set Up Debug wizard opens, as shown in the following figure.

  4. Click Next.

    The Nets to Debug page opens, as shown in the following figure.

  5. Select a subset (or all) of the nets to debug. Every signal must be associated with the same clock in an ILA. If the clock domain association cannot be found by the tool, manually associate those nets to a clock domain by selecting all the nets that have the Clock Domain column specified as undefined or partially defined.
    You need to mark the entire interfaces that you are interested in debugging; however, if you are concerned with device resource usage, then the nets you do not need for debugging can be deleted while setting up the debug core.
  6. To associate a clock domain to the signals that have an undefined or partially defined Clock Domain, select the nets, right-click, and choose Select Clock Domain as shown in the following figure.
    Tip: One ILA is inferred per clock domain by the Set up Debug wizard.

  7. In the Select Clock Domain dialog box, shown in the following figure, select the clock, and click OK.

  8. In the Specify Nets to Debug dialog box, click Next.
  9. In the ILA Core Options page, shown in the following figure, select the appropriate options for triggering and capturing data, and click Next.

    The advanced triggering capabilities provide additional control over the triggering mechanism. Enabling advanced trigger mode enables a complete trigger state machine language that is configurable at run time.

    There is a three-way branching per state and there are 16 states available as part of the state machine. Four counters and four programmable counters are available and viewable in the Analyzer as part of the advanced triggering.

    In addition to the basic capture of data, capture control capabilities let you capture the data at the conditions where it matters. This ensures that unnecessary block RAM space is not wasted and provides a highly efficient solution.

  10. In the Summary page, shown in the following figure, verify that all the information looks correct, and click Finish.

    The Debug window looks like the following figure after the ILA core has been inserted.

    Note: All the buses (and single-bit nets) have been assigned to different probes.

    The probe information also shows how many signals are assigned to that particular probe.

    For example, in the following figure, probe0 has 32 signals (the 32 bits of the microblaze_1_axi_periph_m02_axi_WDATA) assigned.

    You are now ready to implement your design and generate a bitstream.

  11. Select Flow Navigator > Program and Debug, and click Generate Bitstream.

    Because you made changes to the netlist (by inserting an ILA core), a dialog box, as shown in the following figure, displays asking if the design should be saved prior to generating bitstream.

    You can choose to save the design at this point, which writes the appropriate constraints in an active constraints file (if one exists), or create a new constraints file.

    The constraints file contains all the commands to insert the ILA core in the synthesized netlist as shown in the following figure.

    The benefit of saving the project is that if the signals marked for debug remain the same in the original block design, then there is no need to insert the ILA core after synthesis manually as these constraints will take care of it. Therefore, subsequent iteration of design changes will not require a manual core insertion.

    If you add more nets for debug (or unmark some nets from debug) then you must open the synthesized netlist and make appropriate changes using the Set up Debug wizard.

    If you do not chose to save the project after core insertion, none of the constraints show up in the constraints file and you must insert the ILA core manually in the synthesized netlist in subsequent iterations of the design.

    With the debug cores and signal probes inserted into the top-level design, you are ready to debug the design in the Vivado hardware manager. For more information on working with the Vivado hardware manager, and programming and debugging devices, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).