Editing the RTL Module After Instantiation - 2020.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)
Document ID
UG994
Release Date
2021-01-04
Version
2020.2 English

To edit the source code of a module, right-click it, and select Go To Source from the context menu, as shown in the following figure.

Figure 1. Editing an RTL Module After Instantiation

This opens the module source file for editing, shown in the following figure.

Figure 2. Editing Top-Level Source File in the Editor

If you modify the source and save it, notice that the Refresh Changed Modules link becomes active in the banner of the block design canvas, as shown in the following figure.

Figure 3. Updating an RTL Module

Click Refresh Changed Modules to reread the module from the source file. Depending on the changes made to the module definition, for example, adding a new port to the module, you might see a message such as shown in the following figure.

Figure 4. Critical Warning Dialog Box after Updating an RTL Module

On the Tcl console, you see the changes that were made to the module, as shown in the following snippet: 

WARNING: [IP_Flow 19-4698] Upgrade has added port 'new_port'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'module reference design_1_my_dff8_inst_0_0'. These changes may impact your design.
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'module reference design_1_my_dff8_inst_0_0' has identified issues that may require user intervention. 
Please verify that the instance is correctly configured, and review any upgrade messages.