Step 5: Making Incremental Changes - 2020.2 English

Vivado Design Suite Tutorial: Implementation (UG986)
Document ID
UG986
Release Date
2021-02-17
Version
2020.2 English
In this step, you make minor changes to the RTL design sources. These changes necessitate resynthesizing the netlist and re-implementing the design.
  1. In the Hierarchy tab of the Sources window, double-click the top-level VHDL file, core_transform.vhdlunder arnd1, to open the file in the Vivado IDE text editor, as shown in the following figure.

  2. Go to line 65 and make swap the inputs to uReg and xReg. The following code snippet shows the required changes:
    From To 
    
begin
    process (clk)
    begin
    if rising_edge(clk) then
         xStepReg <= xStep;
          uReg <= u;
          xReg <= x;
    end if;
    end process;
    		 
     
begin
    process (clk)
    begin
    if rising_edge(clk) then
         xStepReg <= xStep;
          --uReg <= u;
          --xReg <= x;
          uReg <= x;
          xReg <= u;
    end if;
    end process;
  3. Save the changes by clicking the Save File button in the toolbar of the text editor.

    As you can see in the following figure, changing the design source files also changes the run status for finished runs from Complete to Out-of-date.