Step 5: Test the Design in Hardware - 2020.2 English - Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions.

Step 5: Test the Design in Hardware - 2020.2 English - Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions. - UG947

Vivado Design Suite Tutorial: Dynamic Function eXchange

Document ID

UG947

Release Date

2021-02-23

Version

2020.2 English

With a set of full and partial bitstreams created, the design can be tested on one of the four demonstration boards. The current design supports the KCU105, VCU108, KCU116, and VCU118 boards, revisions Rev 1.0 and newer.