Step 4: Assembling and Implementing the Design - 2020.2 English - Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions.

Step 4: Assembling and Implementing the Design - 2020.2 English - Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions. - UG947

Vivado Design Suite Tutorial: Dynamic Function eXchange

Document ID

UG947

Release Date

2021-02-23

Version

2020.2 English

Now that the synthesized checkpoints for each module, plus top, are available, you can assemble the design. You will run all flow steps from the Tcl Console, but you can use features within the IDE (such as the floorplanning tool) for interactive events.