Partially Reconfiguring the Device - 2020.2 English - Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions.

Partially Reconfiguring the Device - 2020.2 English - Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions. - UG947

Vivado Design Suite Tutorial: Dynamic Function eXchange

Document ID

UG947

Release Date

2021-02-23

Version

2020.2 English

At this point, you can partially reconfigure the active device with any of the partial bitstreams that you have created, but only if it is compatible with the currently loaded design. For UltraScale devices, you must always first start with the appropriate clearing bitstream(s). Because of this, the following section is split by family, as UltraScale+ instructions are simpler. The instructions below have been separated by family for clarity.