Complete Hardware Validation - Complete Hardware Validation - 2020.2 English - Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions.

Complete Hardware Validation - Complete Hardware Validation - 2020.2 English - Describes the recommended design methodology to achieve efficient utilization of Xilinx® FPGA device resources, and quicker design implementation and timing closure in Vivado® Design Suite. Provides the reasons behind the recommended method to support and enable informed design decisions. - UG947

Vivado Design Suite Tutorial: Dynamic Function eXchange

Document ID

UG947

Release Date

2021-02-23

Version

2020.2 English

With all full and partial bitstreams generated, PROM file generation can be done. The bitstreams are named and located in the same way as was done in Lab 7, so this design testing can be completed in that lab. Return to Lab 7, Step 2, Instruction 25 to complete the hardware testing.