Vivado Design Suite Tutorial: Using Constraints (UG945) - 2020.2 English - Introduces the use of Xilinx Design Constraints (XDC), and Tcl commands, to define and configure an FPGA design in the Vivado Design Suite. Accurate timing constraints are vital to meet design goals and ensure design performance throughout synthesis and implementation. - UG945

Document ID

UG945

Release Date

2021-02-08

Version

2020.2 English