Working with Constraints - 2020.2 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
Release Date
2020.2 English

The Vivado IDE supports the Xilinx design constraint (XDC) and Synopsys design constraint (SDC) file formats. The SDC format is for timing constraints while the XDC format is for both timing and physical constraints. Constraints can include placement, timing, and I/O restrictions. You can create constraints during various steps in the design flow, including RTL analysis, synthesis, and implementation. For more information on constraint files, constraint sets, and the various types of constraints, refer to Vivado Design Suite User Guide: Using Constraints (UG903).

The Vivado Design Suite provides flexibility in defining and using constraints in a project. You can use a single XDC file to add and maintain the design constraints, or you can use multiple XDC files to organize the constraints into separate files. You can create multiple constraint sets to experiment with various types of constraints, or store multiple versions of constraints. Each constraint set can contain one or more constraint files.

The Vivado Design Suite also lets you define constraints in Tcl scripts which can either be sourced in the Tcl shell or Tcl console, or added to a constraint set in your design. Defining constraints in Tcl scripts allows you to use standard Tcl commands as part of the constraint scope and definition. However, defining constraints in Tcl scripts also has certain limitations, such as not being able to save changes to design constraints back to the source Tcl script.

Note: For more information on working with Tcl scripts, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).

You can open multiple designs referencing a single constraint set. However, you must be careful to manage changes made to multiple designs that reference the same constraint set. If the Vivado IDE detects unsaved changes in multiple open designs, it prompts you to select which design to save to the referenced constraint file.

When saving constraints files, be careful not to overwrite any unsaved constraint definitions in an unsaved design.

An implemented design saves a snapshot of the constraints used during the implementation run along with a reference to the original constraint file lines. When opening an implemented design, the constraints loaded from the implementation run might be older than the implementation constraints from the constraints set in the project. This can cause the loss of newer constraints in the project constraint files when you save the design from an implemented run after adding or editing the constraints in memory. Generally, the Vivado IDE manages these revision issues and prompts you to take the appropriate action as needed. However, you should be aware of the potential conflict between the constraints in memory and the constraints files in the constraints set associated with the implementation run.

In the Vivado IDE, the following windows enable you to create and work with constraints:

Timing Constraints Window
Shows all XDC file timing constraints for the project in a table format. You can an interactively edit existing constraints, which are saved back to the source file, or create new constraints.
Device Constraints Window
Enables you to set various SelectIO™ interface constraints on displayed banks.
Physical Constraints Window
Enables you to create and manage Pblocks.
Tip: Select Tools > Timing > Constraints Wizard on a synthesized design to create a top-level XDC file based on design methodologies recommended by Xilinx. The wizard guides you through specifying clocks, setting up input and output constraints, and properly constraining cross-clock domain clock groups.
Video: See the Vivado Design Suite QuickTake Video: Using the Vivado Timing Constraint Wizard for an introduction to using the Timing Constraints Wizard.