Using HDL Language Templates - 2020.2 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
Release Date
2020.2 English

The Vivado IDE provides templates for many Verilog, VHDL, and XDC structures, including Xilinx Parameterized Macros (XPMs) and library primitives. To view the templates:

  1. In the Vivado IDE Text Editor, select the Language Templates toolbar button.
  2. Select Tools > Language Templates.

    The Language Templates window appears with folders for Verilog, VHDL, SystemVerilog, XDC, and Debug.

    Figure 1. Language Templates Window

When a template is selected, you can use the Insert Template command from the popup menu in the Text Editor. Selecting this command copies the currently selected template text into the file being edited, at the current location of the cursor. Alternatively, you can highlight, and then copy and paste the desired text from the Language Templates window. For supported commands, see this link in the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).