Overview - 2020.2 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
Release Date
2020.2 English

Debugging an FPGA design is a multi-step, iterative process. Like most complex problems, it is best to break the FPGA design debugging process down into smaller parts, for example, by focusing on making a smaller section of the design work rather than trying to make the whole design work at one time. An example of a proven design and debug methodology is to iterate through the design flow, adding one module at a time and making it function properly in the context of the whole design. You can use this design and debug methodology in any combination of the following design flow stages:

  • RTL-level design simulation
  • In-system debugging

In addition to using the Set up Debug wizard, you can also use Tcl commands to create, connect, and insert debug cores into your synthesized design netlist. For more information on debugging, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).