IP Bus Interfaces with Tri-state Ports - 2020.2 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2021-02-12
Version
2020.2 English

IP bus interface exposes three signals (I, O, and T) for tri-state ports. Based on the IP configuration, one or all three signals are exposed as single external ports via the tri-state buffer.

In the interface logical to physical port mapping, <port_map>, section only the exposed signal needs to be defined for GPIO, whereas for IO all three signals need to be mapped to a physical port.

Example

<interface mode="master" name="dip_switches_4bits" 
type="xilinx.com:interface:gpio_rtl:1.0">
      <port_maps>
        <port_map logical_port="TRI_I" physical_port="dip_switches_tri_i"/>
      </port_maps>
</interface>
<interface mode="master" name="iic_main" type="xilinx.com:interface:iic_rtl:1.0">
      <port_maps>
        <port_map logical_port="SDA_I" physical_port="iic_main_sda_i"/>
        <port_map logical_port="SDA_O" physical_port="iic_main_sda_o"/>
        <port_map logical_port="SDA_T" physical_port="iic_main_sda_t"/>
        <port_map logical_port="SCL_I" physical_port="iic_main_scl_i"/>
        <port_map logical_port="SCL_O" physical_port="iic_main_scl_o"/>
        <port_map logical_port="SCL_T" physical_port="iic_main_scl_t"/>
      </port_maps>
</interface>