Generating Output Products for Block Designs - 2020.2 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
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2020.2 English

Once the block design is complete and the design is validated, output products must be generated to support the block design throughout the design flow. These output products include files such as a Verilog or VHDL instantiation template, or HDL wrapper files, to facilitate integrating the block design into the current project, design constraints files (XDC) that are included to provide timing or physical constraints for the block design, and synthesized netlists or design checkpoints to support the block design.

The output products for a block design are generated in the target language of the current project. If the source files for a particular IP used in the block design cannot be generated in the target language, a message is returned to the Tcl Console, and the output products will be generated in the available or supported language.

To generate output products, right-click on the block design and select the Generate Output Products command, or select Generate Block Design from the Flow Navigator.

The Generate Output Products dialog box is displayed as shown below.

Figure 1. Generate Output Products—Block Design

Generating the output products also generates the top level netlist of the block design. The netlist is generated in either VHDL or Verilog depending on the target language settings for the current project.

By default, synthesized design checkpoint (DCP) files are created for each IP inside the Block Design to speed up synthesis times. You can change the synthesis mode by selecting the Out of context per Block Design radio button on the Generate Output Products dialog box. For more information, on the using the Out-of-Context flow see this link in the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994).

Once the Block Design is created and generated you need to then instantiate it into your design by selecting either the Block Design, RMB > Create Wrapper or by instantiating the Block Design in your own RTL. During creation the dialog box will appear.

Figure 2. Create HDL Wrapper

If you want to modify the wrapper, select the Copy Generated Wrapper to allow user edits, otherwise select Let Vivado Manage Wrapper to auto-update.