Components - 2020.2 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
Release Date
2020.2 English
Important: The <component> section forms a very important part of the board file because it defines the components found on the board, as well as different operating modes of the components, and the settings needed to enable these modes.

This section gives a list of all the components present on the board, as well as details such as part name, type of component, and vendor. Some examples of components include Xilinx FPGA, DDR3, Quad SPI flash, Ethernet Phy, LED, and DIP Switches. The <components> section includes one or more nested <component> tags.

  <component name="part0" display_name="Kintex-7 KC705 Evaluation Platform"
  type="fpga" part_name="xc7k325tffg900-2" pin_map_file="part0_pins.xml"
  vendor="xilinx" spec_url="">
    <description>FPGA part on the board</description>
  <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr3"
  major_group="External Memory" part_name="MT8JTF12864HZ-1G6G1" vendor="Micron"
    <description>1 GB DDR3 memory SODIMM </description>

In the KC705 board file the first declared component is "part0", which is the Xilinx FPGA device. Xilinx devices on the board, listed as “fpga” type components, should be named sequentially starting with part0. Additional <component> elements define the other components on the board, and any interfaces needed to connect from the Xilinx device to the board component.

The different attributes and <tags> of the <component> tag are explained in the following table:

Table 1. <component> Attribute and Tags
Tag Usage/Description Example (KC705)
name= Name of the component. name="part0"
display_name= The name displayed in the Board tab of the Vivado IP integrator. display_name="Kintex-7 KC705 Evaluation Platform"

Type of part:

“fpga” - Specifies the Xilinx FPGA parts on the board.

“chip” - Defines all components which have a chip on the board, except FPGAs or FMC connectors. Examples of chips include ddr3_sdram and linear_flash.

“connector” - Defines FPGA Mezzanine Card (FMC) connectors.

sub_type= Subtype of the component sub_type="ethernet"
major_group= Major group that the component is a part of. The Board tab in the Vivado IP integrator organizes components of the board according to the major_group. See Components. major_group="ethernet"

Part identifier.

For type=fpga, the part_name must be a valid Xilinx supported part, or the board files will not be loaded into the Vivado Design Suite.

pin_map_file= A file where the constraints for each pin are provided. Refer to Pin Map for more information. pin_map_file="part0_pins.xml"
vendor= Vendor of the part. vendor="xilinx"
spec_url= URL for the device specification or other information related to the part. spec_url=""
<description> Short description of the component. <description> FPGA device on the board. </description>
<parameters> Lists parameter name and value pairs. Refer to Parameters for details and examples.
<pins> List of pins identified for the component. See Pins for details and examples.
<component_modes> Modes specific to the defined <component>. See Component Modes for details and examples.
<interfaces> Defines the interfaces implemented by the specified component. See Interfaces for more information and examples.

The <components> defined in the Board file are listed in the Board tab of the Vivado IP Integrator, as shown in Components. The components are grouped according to the 'major_group=' attribute of the <component> element, and the ‘display_name=’ is displayed.

Figure 1. Board Window in Vivado IP Integrator

Double-clicking a component in the Board tab opens the Connect Board Component dialog box in the Vivado IP integrator. This lets you select the preferred IP to add into the design canvas of the block diagram, to implement the necessary signal interfaces to connect to the component on the board.