By default, Vitis HLS uses the same
clock for the AXI4-Lite
interface and the synthesized design. Vitis HLS connects all registers in the AXI4-Lite interface to the clock used for
the synthesized logic (ap_clk).
Optionally, you can use the INTERFACE directive clock option to specify a
separate clock for each AXI4-Lite port. When connecting the clock
to the AXI4-Lite interface,
you must use the following protocols:
-
AXI4-Lite
interface clock must be synchronous to the clock
used for the synthesized logic (
ap_clk). That is, both clocks must be derived from the same master generator clock. -
AXI4-Lite
interface clock frequency must be equal to or less
than the frequency of the clock used for the
synthesized logic (
ap_clk).
If you use the clock
option with the INTERFACE directive, you only need to specify
the clock option on one
function argument in each bundle. Vitis HLS implements all other function
arguments in the bundle with the same clock and reset. Vitis HLS names the
generated reset signal with the prefix ap_rst_ followed by the clock name. The
generated reset signal is active-Low independent of the config_rtl command.
The following example shows how Vitis HLS groups function arguments
a and b into an AXI4-Lite port with a
clock named AXI_clk1 and an
associated reset port.
// Default AXI-Lite interface implemented with independent clock called AXI_clk1
#pragma HLS interface s_axilite port=a clock=AXI_clk1
#pragma HLS interface s_axilite port=bIn the following example, Vitis HLS groups function arguments
c and d into AXI4-Lite port CTRL1 with a separate clock
called AXI_clk2 and an
associated reset port.
// CTRL1 AXI-Lite bundle implemented with a separate clock (called AXI_clk2)
#pragma HLS interface s_axilite port=c bundle=CTRL1 clock=AXI_clk2
#pragma HLS interface s_axilite port=d bundle=CTRL1