ap_return for the return value. s_axilite) all the ports in the block-level interface are grouped into the
s_axilite interface. This is a common practice when
another device, such as a CPU, is used to configure and control when the block starts and
stops operation, and is a requirement of XRT.The ap_ctrl_hs block-level I/O protocol is
the default for the Vivado IP flow. Default Interfaces for Vivado IP Flow shows the resulting RTL ports and behavior when
Vitis HLS implements ap_ctrl_hs on a function.
The ap_ctrl_chain control protocol is
similar to ap_ctrl_hs but provides an additional input
signal ap_continue to apply back pressure. Xilinx recommends using the ap_ctrl_chain block-level I/O protocol when chaining Vitis HLS blocks together and is the default for the Vitis Kernel flow. Refer to Supported Kernel Execution Models for more information on how XRT
uses these control protocols.
ap_ctrl_hs
The following figure shows the behavior of the block-level handshake
signals created by the ap_ctrl_hs I/O protocol for a
non-pipelined design.
After reset, the following occurs:
- The block waits for
ap_startto go High before it begins operation. - Output
ap_idlegoes Low immediately to indicate the design is no longer idle. - The
ap_startsignal must remain High untilap_readygoes High. Onceap_readygoes High:- If
ap_startremains High the design will start the next transaction. - If
ap_startis taken Low, the design will complete the current transaction and halt operation.
- If
- Data can be read on the input ports.
- Data can be written to the output ports.Note: The input and output ports can also specify a port-level I/O protocol that is independent of this block-level I/O protocol. For details, see Port-Level I/O Protocols.
- Output
ap_donegoes High when the block completes operation.Note: If there is anap_returnport, the data on this port is valid whenap_doneis High. Therefore, theap_donesignal also indicates when the data on outputap_returnis valid. - When the design is ready to accept new inputs, the
ap_readysignal goes High. Following is additional information about theap_readysignal:- The
ap_readysignal is inactive until the design starts operation. - In non-pipelined designs, the
ap_readysignal is asserted at the same time asap_done. - In pipelined designs, the
ap_readysignal might go High at any cycle afterap_startis sampled High. This depends on how the design is pipelined. - If the
ap_startsignal is Low whenap_readyis High, the design executes untilap_doneis High and then stops operation. - If the
ap_startsignal is High whenap_readyis High, the next transaction starts immediately, and the design continues to operate.
- The
- The
ap_idlesignal indicates when the design is idle and not operating. Following is additional information about theap_idlesignal:- If the
ap_startsignal is Low whenap_readyis High, the design stops operation, and theap_idlesignal goes High one cycle afterap_done. - If the
ap_startsignal is High whenap_readyis High, the design continues to operate, and theap_idlesignal remains Low.
- If the
ap_ctrl_chain
The ap_ctrl_chain block-level I/O
protocol is similar to the ap_ctrl_hs protocol but
provides an additional input port named ap_continue. An
active-High ap_continue signal indicates that the
downstream block that consumes the output data is ready for new data inputs. If the
downstream block is not able to consume new data inputs, the ap_continue signal is Low, which prevents upstream blocks from generating
additional data.
The ap_ready port of the downstream
block can directly drive the ap_continue port. Following
is additional information about the ap_continue port:
- If the
ap_continuesignal is High whenap_doneis High, the design continues operating. The behavior of the other block-level I/O signals is identical to those described in theap_ctrl_hsblock-level I/O protocol. - If the
ap_continuesignal is Low whenap_doneis High, the design stops operating, theap_donesignal remains High, and data remains valid on theap_returnport if theap_returnport is present.
In the following figure, the first transaction completes, and the second
transaction starts immediately because ap_continue is High
when ap_done is High. However, the design halts at the end
of the second transaction until ap_continue is asserted
High.
ap_ctrl_none
If you specify the ap_ctrl_none
block-level I/O protocol, the handshake signal ports (ap_start, ap_idle, ap_ready, and ap_done) are not created. You
can use this protocol to create a block without control signals, as used in free-running
kernels.
ap_ctrl_none block-level I/O protocol on your design,
you must meet at least one of the conditions for C/RTL co-simulation as described in Interface Synthesis Requirements to verify the RTL
design. If at least one of these conditions is not met, C/RTL co-simulation halts with the
following
message:@E [SIM-345] Cosim only supports the following 'ap_ctrl_none' designs: (1)
combinational designs; (2) pipelined design with task interval of 1; (3) designs with
array streaming or hls_stream ports.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***