Generating and Opening the Application Timeline - 2020.2 English - UG1393

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)
Document ID
UG1393
Release Date
2021-03-22
Version
2020.2 English

To generate the Application Timeline report, you must complete the following steps to enable timeline and device trace data collection in the command line flow:

  1. Instrument the FPGA binary during linking, by adding Acceleration Monitors and AXI Performance Monitors to kernels using the v++ --profile option as described in --profile Options. As an example, add --profile.data to the v++ linking command line: 
    v++ -g -l --profile.data all:all:all ...
  2. After the kernels are instrumented during the build process, data gathering must also be enabled during the runtime execution of the application by editing the xrt.ini file. Refer to xrt.ini File for more information.

    The following xrt.ini file will enable maximum information gathering when the application is run:

    [Debug]
profile=true
timeline_trace=true
data_transfer_trace=coarse
stall_trace=all
    Tip: If you are collecting a large amount of trace data, you might need to use the --trace_memory with the v++ command, and the trace_buffer_size keyword in the xrt.ini.

    After running the application, the Application Timeline data is captured in a CSV file called timeline_trace.csv.

  3. The CSV report can be viewed in the Vitis analyzer tool by opening the Run Summary produced during the application execution. You can launch the Vitis analyzer and open the Run Summary using the following command:
    vitis_analyzer <project>.run_summary