Description
The design requires more synchronous storage elements than are available. The total number of registers required by all kernels is more than the number available on the device.
Explanation
CPUs contain an internal set of registers keeping input and output values of the basic operations of the arithmetic logical unit. When an algorithm is implemented in hardware on and FPGA, storage of intermediate values is required if the sequence of operations spawns multiple cycles. As a result, any design but the simplest, will require registers for storage of intermediate values.
When this message is issued, the number of registers (synchronous storage elements) exceeds the number available on the device. It will therefore be necessary to reduce the number of registers required for the implementation of the algorithm.
Recommendation
There are many ways to influence the register count of an implementation. To best gauge how to reduce the total number, you should understand how many registers are utilized where. You can find this information in the HLS report or by studying the dependencies in the HLS Schedule viewer. With this information, you can then decide whether restructuring the algorithm, mapping registers to memory, or simply reducing the datapath width can reduce the overall resource utilization.