Description
PCIe® transfer of data to FPGA is suboptimal. This is flagged when the transfer rate from Host to FPGA is less than 70% of the maximum possible write transfer bandwidth of PCIe.
Explanation
XRT computes all the data transfer from PCIe to FPGA over a period of time and calculates the Bandwidth utilization of PCIe write transfer.
There are several factors that can reduce the write transfer utilization of PCIe. These could be one of the following:
- The host using small buffers
- DDR Contention from Host writing data to DDR and Kernel writing data to the same DDR
- The host sending several smaller transfers
Resolution
It is recommended to aggregate the data to be transferred in single buffer and send it over PCIe to DDR. PCIe BW is usually reasonable if the buffer size to be transferred is about 4kB. To avoid DDR contentions from Host and Kernel writing to same DDR, multiple DDR banks can be utilized as well.