Kernel to DDR Connection - 2019.2 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2019-10-30
Version
2019.2 English

Description

This rule checks and informs the user that the DDR connected to the kernel is not in the same or adjacent SLR.

Explanation

Kernel compute unit (CU) instance and DDR memory resource floorplanning are keys to meeting the quality of results of your design in terms of frequency and resources. Floorplanning involves explicitly allocating CUs (a kernel instance) to SLRs and mapping CUs to DDR memory resources. When floorplanning, both CU resource usage, and DDR memory bandwidth requirements need to be considered

The largest Xilinx® FPGAs are made up of multiple stacked silicon dies. Each stack is referred to as a super logic region (SLR) and has a fixed amount of resources and memory including DDR interfaces. You can use the actual kernel resource utilization values to help distribute CUs across SLRs to reduce congestion in any one SLR.

The less congestion in an SLR, the better the tools can map the design to the FPGA resources and meet your performance target.

For more information, refer to Optimizing the Performance in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).

Resolution

For better performance, it is strongly recommended to have kernels connect to DDR interfaces within the same SLR or a neighboring SLR.

For example. If Kernel is in SLR0 it should be connected to DDR in either SLR0 or SLR1.