DDR Bank Connections - 2019.2 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2019-10-30
Version
2019.2 English

Description

This rule checks the number of compute unit ports connected to all DDR banks on the device.

Explanation

Multiple compute unis when connected to the same DDR bank, the bandwidth will be shared among the N compute units. This creates memory stalls on the system and reduces the performance of the application.

Recommendation

Please connect different compute units to different DDR banks to improve the system performance.