Dual Clock Mode - 2.6 English

Semi-Ternary CAM Search v2.6 LogiCORE IP Product Guide (PG319)

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2.6 English

In dual clock mode, the internal RAM and match logic is clocked on a separate high frequency clock ram_clk. This enables a high TDM_FACTOR to be used without increasing the frequency of the Lookup Interface.

Note: Both ram_clk and key_clk must be derived from the same PLL to avoid clock drift.