Clocking - 2.6 English

Semi-Ternary CAM Search v2.6 LogiCORE IP Product Guide (PG319)

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2.6 English

All timing analysis has been performed on -2M speed grade. The CAM clock domains are shown in the following table.

Table 1. Clocks
Clock Description
s_axi_aclk The AXI clock is used for table management. The AXI management interface has a completely asynchronous relationship with the lookup interface.
key_clk AXI4-Stream clock for Lookup Request/Response interfaces.
ram_clk The ram_clk is optional. It provides an option to clock the internal RAM and match logic on a separate high frequency clock. In most cases, this saves logic and memory resources.


  • key_clk <= 300 MHz, use ram_clk up to 600 MHz.
  • key_clk > 300 MHz, ram_clk is not used.