System Interface Ports - 2.5 English

Semi-Ternary CAM Search v2.5 LogiCORE IP Product Guide (PG319)

Document ID
PG319
Release Date
2023-05-16
Version
2.5 English
Table 1. System Interface
Port Name I/O Clock Description
rstn I   Asynchronous reset (active_low). The reset input is synchronized internally to both the ram_clk and key_clk domains.
rst_busy O s_axi_aclk Reset Busy is an active-High indicator that the core is currently in reset state.
ram_clk I   The ram clock is used for the internal RAM and match logic.
sbiterr O key_clk Single-bit error output status. A single-bit error has been detected and corrected by the ECC scrubbing mechanism. The outputs are not triggered by lookup operations, only activated when the ECC scrubber runs every 1 ms.
dbiterr O key_clk Double-bit error output status. A double-bit error has been detected by the ECC scrubbing mechanism. The outputs are not triggered by lookup operations, only activated when the ECC scrubber runs every 1 ms.
debug_status[31:0] O   Debug status port.