Single Clock Mode - 2.5 English

Semi-Ternary CAM Search v2.5 LogiCORE IP Product Guide (PG319)

Document ID
PG319
Release Date
2023-05-10
Version
2.5 English

Single clock mode is activated by specifying the same value for both LOOKUP_INTERFACE_FREQ and RAM_FREQ. The ram_clk port is not used in single clock mode. The Lookup interfaces, internal RAM and match logic are all clocked on the key_clk.

Note: Single clock mode is recommended for Lookup rates above 300 Mlps.