IP Facts - 2.5 English

Semi-Ternary CAM Search v2.5 LogiCORE IP Product Guide (PG319)

Document ID
PG319
Release Date
2023-05-16
Version
2.5 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 AMD UltraScale+™ , AMD UltraScale™ , AMD Zynq™ AMD UltraScale+™ , AMD Versal™ adaptive SoC
Supported User Interfaces AXI4-Stream and AXI4-Lite Interfaces
Resources See the CAM Configuration section in the Main Tab topic.
Provided with Core
Design Files Encrypted Verilog RTL
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraint (XDC)
Simulation Model Verilog source code
Supported S/W Driver 2 Standalone
Software Example Design Application Standalone, AMD Vivado™ IP integrator
Tested Design Flows 3
Design Entry 4 Standalone, VitisNetP4, AMD Vivado™ IP integrator.
Simulation 5 For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis AMD Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: N/A
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. Standalone driver details can be found online.
  3. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
  4. The CAM IP is only supported in the Vivado IP Catalog running on a Linux operating system (not supported on Windows).
  5. Modelsim, Questa, VCS, Xcelium, and Xsim are supported. Refer to Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for information on version compatibility.