The CAM IP generator core provides a quick way to simulate and observe the behavior of the core by using the provided example design, which has a self-checking testbench that uses System Verilog Direct Programming Interface (DPI). It is recommended that you familiarize yourself with Section 35 of IEEE 1800-2017 to gain a more complete understanding of its functionality.
- In the new Example Design Vivado
project, change the target simulator:
- Click Settings under the PROJECT MANAGER section in the left-hand panel. The Settings window displays.
- Select Simulation
under Project Settings, and select the target simulator you want to use, as
shown in the following figure.
- Verify that the compiled library location is set correctly and points to the correct pre-compiled simulation libraries for the simulator being used. See the Vivado Design Suite User Guide: Logic Simulation (UG900) for instructions on how to compile simulation libraries.
Note: When the example design for the
CAM IP is generated, a simulation SystemVerilog package file is also created with the
name <instance-name>_sim_pkg.sv. This file
contains the SystemVerilog task
create which contains
the configuration settings used for this particular CAM IP instance.Optional Features
- Backdoor feature
- This feature speeds up simulation runtime when enabled for behavioral
simulations only. This feature is disabled by default. To enable this
feature, perform the following edit to the file:
- axi_lite_master.sv
- Set the define CAM_BACKDOOR
- Dump Memory feature
- This feature allows memory contents to be dumped at the end of the test for
behavioral simulations only. This feature is disabled by default. To enable
this feature, perform the following edit to the file:
- example_top.sv
- Set the parameter DUMP = 1;