Product Specification - 2.4 English

Ternary CAM Search LogiCORE IP Product Guide (PG318)

Document ID
PG318
Release Date
2022-11-08
Version
2.4 English

The functional block diagram of the core is shown in the following figure.

Figure 1. Core Block Diagram
The previous figure contains the following sub-blocks:
CAM Database
Memory and registers for storage of rules and logic for algorithmic lookup matching.
Lookup Request FIFO (Optional)
Transfers Lookup Requests from the Lookup Frequency domain to the RAM Frequency domain.
Lookup Response FIFO (Optional)
Transfers Lookup Responses from the RAM Frequency domain to the Lookup Frequency domain.
Management Request FIFO
Buffering queue for input Management Requests.
Management Response FIFO
Buffering queue for Management Responses.
Strict Priority Scheduler
Schedules lookup and Management Requests.
AXI4-Lite interface slave
Protocol handling for accepting read/write requests and generating responses. The AXI4-Lite interface uses 13 bits of address and 32 bits of data.

The following clock domains are depicted in the block diagram:

AXI4-Stream Lookup Interface Frequency
The clock frequency of the Lookup Request/Response interfaces. Depending on configuration parameters a new Lookup Request may arrive every cycle, every second cycle, every fourth cycle, etc.
RAM Frequency
The clock frequency of the internal RAM and match logic.
AXI4-Lite Frequency
The clock frequency of the AXI Lite bus.

The clocking of the CAM can be set to one of two modes:

Single Clock Mode
If the Lookup Interface Frequency and RAM Frequency are equal, then the RAM clock is not used and the Lookup Request/Response FIFOs are removed completely.
Dual Clock Mode
If the RAM Frequency is higher than the Lookup Interface Frequency, shallow FIFOs are inserted to bridge the clock domains.