General Checks - 2.4 English

Ternary CAM Search LogiCORE IP Product Guide (PG318)

Document ID
PG318
Release Date
2022-11-08
Version
2.4 English
Ensure that all the timing constraints for the core were properly incorporated and that all constraints were met during implementation.
  • Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
  • If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.
  • If your outputs go to 0, check your licensing.