Dual Clock Mode - 2.4 English

Ternary CAM Search LogiCORE IP Product Guide (PG318)

Document ID
PG318
Release Date
2022-11-08
Version
2.4 English

In dual clock mode, the internal RAM and match logic is clocked on a separate high frequency clock ram_clk. This enables a high TDM_FACTOR to be used without increasing the frequency of the Lookup Interface.

Note: Both ram_clk and key_clk must be derived from the same PLL to avoid clock drift.