Single Clock Mode - 2.4 English

Binary CAM Search LogiCORE IP Product Guide (PG317)

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2.4 English

Single clock mode is activated by specifying the same value for both LOOKUP_INTERFACE_FREQ and RAM_FREQ. The ram_clk port is not used in single clock mode. The Lookup interfaces, internal RAM and match logic are all clocked on the key_clk.

Note: Single clock mode is recommended for Lookup rates above 300 Mlps.