Features - 2.4 English

Binary CAM Search LogiCORE IP Product Guide (PG317)

Document ID
Release Date
2.4 English
  • Associative array containing arbitrary (key, response) entries.
  • Exact match key lookup returns hit/miss result and associated response value on hit.
  • High throughput: one lookup per clock cycle up to 600 MHz.
    Note: Achievable clock frequencies will depend on the device being used, the resources used by the CAM configuration, and the congestion in the device.
  • Flexible, supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
  • Supports all key widths up to 992 bits and all response widths up to 1024 bits.
  • Supports both UltraRAM (URAM) and block RAM implementations.
  • Scalable, supports one or multiple BCAM instances, each instance can use all block RAM/UltraRAM (URAM) within an SLR allowing very large BCAMs.
  • High storage efficiency, 95% of the RAM bits are transformed to CAM bits.
  • Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with patrol scrubbing.
  • Supports Vivado® IP integrator.
  • Supports entry insert, delete, update using standard TCAM like software APIs.
  • CBCAM supports entry insert and delete through a hardware port without use of software.
  • Can be inferred from within P4 code using the Vitis™ Networking P4 (VitisNetP4) tool.