Top-Level Registers - 2.4 English

0x0000

Control

R/W

Bit [0] = ap_start (R/W/COH) ⁽¹⁾

Bit [1] = ap_done (R/COR)

Bit [2] = ap_idle (R)

Bit [3] = ap_ready (R)

Bit [5] = Flush pending AXI transactions (R/W)

Bit [6] = Flush done (R)

Bit [7] = auto_restart (R/W)

Others = reserved

0x0004

Global Interrupt Enable

R/W

Bit [0] = Global interrupt enable

Others = Reserved

0x0008

IP Interrupt Enable

R/W

Bit [0] = ap_done

Bit [1] = ap_ready

Others: reserved

0x000c

IP Interrupt Status

R/TOW ⁽¹⁾

Bit [0] = ap_done

Bit [1] = ap_ready

Others: reserved

0x0010

Width

R/W

Active width of stream on s_axis_video or m_axis_video

0x0018

Height

R/W

Active height of stream on s_axis_video or m_axis_video

0x0020

Stride

R/W

Active stride (in bytes)

0x0028

Memory Video Format

R/W

Active video format of data in memory

0x0030

Plane 1 Buffer

R/W

Start address of plane 1 of frame buffer

0x003C

Plane 2 Buffer

R/W

Start address of plane 2 of frame buffer. Only valid when a semi-planar video format is selected.

0x0048

Field ID

R/W

Field polarity. Only valid for interlaced video.

0x0050

Fid Output Mode

R/W

Applicable for Frame buffer read IP only. Defines the field_id toggle mode.

Bit [1:0]: 0 = Default mode. The field_id signal will be based on the field ID value defined in register 0x0048.

Bit [1:0]: 1 = For first field, the field_id signal is low. After that for each field, the field_id toggles

Bit [1:0]: 2 = The first two fields, the field_id signal is low. After that for each field the field id toggles.

0x0054

Frame Buffer Write Plane 3 Buffer

R/W

Start address of plane 3 of frame buffer. Only valid when a 3 planar video format is selected.

0x0058

fid error

R

Applicable for frame buffer read IP only.

Generates error for the discrepancy of the Field ID register and field_id signal.

Bit[0]: Error bit

0x0074

Frame Buffer Read Plane 3 Buffer

R/W

Start address of plane 3 of frame buffer. Only valid when a 3 planar video format is selected.

Notes:

1. COH = Clear on Handshake, COR = Clear on Read, TOW = Toggle on Write

2. Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in section S_AXILITE Control Register Map of Vitis High-Level Synthesis User Guide (UG1399) [Ref 10] . These registers definitions may have some additional bits; however, in the current IP, we are accessing only bits mentioned in Table: Top-Level Registers . Therefore, only these bits need to be considered while accessing the Control Register, Global Interrupt Enable Register, IP Interrupt Enable Register, and IP Interrupt Status Register.